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? 2006 microchip technology inc. preliminary ds41270b pic10f220/222 data sheet 6-pin, 8-bit flash microcontrollers
ds41270b-page ii preliminary ? 2006 microchip technology inc. information contained in this publication regarding device applications and the like is provi ded only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2006, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2006 microchip technology inc. preliminary ds41270b-page 1 pic10f220/222 device included in this data sheet: ?pic10f220 ?pic10f222 high-performance risc cpu: ? only 33 single-word instructions to learn ? all single-cycle instructions except for program branches which are two-cycle ? 12-bit wide instructions ? 2-level deep hardware stack ? direct, indirect and relative addressing modes for data and instructions ? 8-bit wide data path ? 8 special function hardware registers ? operating speed: - 500 ns instruction cycle with 8 mhz internal clock -1 s instruction cycle with 4 mhz internal clock special microcontroller features: ? 4 or 8 mhz precision internal oscillator: - factory calibrated to 1% ? in-circuit serial programming? (icsp?) ? in-circuit debugging (icd) support ? power-on reset (por) ? short device reset timer, drt (1.125 ms typical) ? watchdog timer (wdt) with dedicated on-chip rc oscillator for reliable operation ? programmable code protection ? multiplexed mclr input pin ? internal weak pull-ups on i/o pins ? power-saving sleep mode ? wake-up from sleep on pin change low-power features/cmos technology: ? operating current: - < 170 a @ 2v, 4 mhz ? standby current: - 100 na @ 2v, typical ? low-power, high-speed flash technology: - 100,000 flash endurance - > 40-year retention ? fully static design ? wide operating voltage range: 2.0v to 5.5v ? wide temperature range: - industrial: -40 c to +85 c - extended: -40 c to +125 c peripheral features: ? 4 i/o pins: - 3 i/o pins with individual direction control - 1 input only pin - high current sink/source for direct led drive - wake-on-change - weak pull-ups ? 8-bit real-time clock/counter (tmr0) with 8-bit programmable prescaler ? analog-to-digital (a/d) converter: - 8-bit resolution - 2 external input channels - 1 internal input channel dedicated device program memory data memory i/o timers 8-bit 8-bit a/d (ch) flash (words) sram (bytes) pic10f220 256 16 4 1 2 pic10f222 512 23 4 1 2 6-pin, 8-bit flas h microcontrollers
pic10f220/222 ds41270b-page 2 preliminary ? 2006 microchip technology inc. pin diagrams pic10f220/222 1 2 3 6 5 4 gp0/an0/icspdat v ss gp1/an1/icspclk gp3/mclr /v pp v dd gp2/t0cki/f osc 4 6-lead sot-23 gp2/t0cki/f osc 4 n/c n/c 8-lead dip pic10f220/222 1 2 3 4 8 7 6 5 v dd gp3/mclr /v pp v ss gp0/an0/icspdat gp1/an1/icspclk
? 2006 microchip technology inc. preliminary ds41270b-page 3 pic10f220/222 table of contents 1.0 general description......................................................................................................... ............................................................. 5 2.0 device varieties ........................................................................................................... ............................................................... 7 3.0 architectural overview ...................................................................................................... ........................................................... 9 4.0 memory organization ......................................................................................................... ........................................................ 13 5.0 i/o port .................................................................................................................... ................................................................... 21 6.0 tmr0 module and tmr0 register............................................................................................... .............................................. 25 7.0 analog-to-digital (a/d) converter ........................................................................................... .................................................... 29 8.0 special features of the cpu................................................................................................. ................................................... 33 9.0 instruction set summary ..................................................................................................... ....................................................... 43 10.0 electrical characteristics ................................................................................................. ........................................................... 51 11.0 development support........................................................................................................ ......................................................... 61 12.0 dc and ac characteristics graphs and charts ................................................................................ ......................................... 65 13.0 packaging information...................................................................................................... .......................................................... 67 index .......................................................................................................................... .......................................................................... 71 the microchip web site ......................................................................................................... .............................................................. 73 customer change notification service ........................................................................................... ..................................................... 73 customer support............................................................................................................... ................................................................. 73 reader response ................................................................................................................ ................................................................ 74 product identification system .................................................................................................. ............................................................ 75 to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro - chip products. to this end, we will continue to improve our publications to better su it your needs. our publications will be re fined and enhanced as new volumes and updates are introduced. if you have any questions or comments regard ing this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) ? the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de lit- erature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
pic10f220/222 ds41270b-page 4 preliminary ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. preliminary ds41270b-page 5 pic10f220/222 1.0 general description the pic10f220/222 devices, from microchip technology, are low-cost, high-performance, 8-bit, fully-static flash-based cmos microcontrollers. they employ a risc architecture with only 33 single-word/ single-cycle instructions. all instructions are single- cycle (1 s) except for program branches, which take two cycles. the pic10f220/222 devices deliver perfor- mance in an order of magnitude higher than their com- petitors in the same price category. the 12-bit wide instructions are highly symmetrical, resulting in a typical 2:1 code compression over other 8-bit microcontrollers in its class. the easy-to-use and easy- to-remember instruction set reduces development time significantly. the pic10f220/222 products are equipped with spe- cial features that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminates the need for the external reset circuitry. intosc internal oscillator mode is pro- vided, thereby, preserving the limited number of i/o available. power-saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the pic10f220/222 devices are available in cost- effective flash, which is suitable for production in any volume. the customer can take full advantage of microchip?s price leadership in flash programmable microcontrollers while benefiting from the flash programmable flexibility. the pic10f220/222 products are supported by a full- featured macro assembler, a software simulator, an in- circuit debugger, a ?c? compiler, a low-cost development programmer and a full featured program- mer. all the tools are supported on ibm ? pc and compatible machines. 1.1 applications the pic10f220/222 devices fit in applications ranging from personal care appliances and security systems to low-power remote transmitters/receivers. the flash technology makes customizing application programs (transmitter codes, appliance settings, receiver fre- quencies, etc.) extremely fast and convenient. the small footprint packages, for through hole or surface mounting, make these microcontrollers well suited for applications with space limitations. low-cost, low- power, high-performance, ease-of-use and i/o flexibil- ity make the pic10f220/222 devices very versatile, even in areas where no microcontroller use has been considered before (e.g., timer functions, logic and plds in larger systems and coprocessor applications). table 1-1: pic10f220/222 devices (1), (2) pic10f220 pic10f222 clock maximum frequency of operation (mhz) 8 8 memory flash program memory 256 512 data memory (bytes) 16 23 peripherals timer module(s) tmr0 tmr0 wake-up from sleep on pin change yes yes analog inputs 2 2 features i/o pins 3 3 input only pins 1 1 internal pull-ups yes yes in-circuit serial programming? yes yes number of instructions 33 33 packages 6-pin sot-23, 8-pin dip 6-pin sot-23, 8-pin dip note 1: the pic10f220/222 devices have power-on reset, selectable watchdog timer, selectable code-protect, high i/o current capability and prec ision internal oscillator. 2: the pic10f220/222 devices use serial programming with data pin gp0 and clock pin gp1.
pic10f220/222 ds41270b-page 6 preliminary ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. preliminary ds41270b-page 7 pic10f220/222 2.0 device varieties a variety of packaging options are available. depend- ing on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic10f220/222 product identification system at the back of this data sheet to specify the correct part number. 2.1 quick turn programming (qtp) devices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program medium-to-high quantity units and whose code patterns have stabilized. the devices are identical to the flash devices but with all flash locations and fuse options already programmed by the factory. certain code and prototype verification procedures do apply before production shipments are available. please contact your local microchip technology sales office for more details. 2.2 serialized quick turn programming sm (sqtp sm ) devices microchip offers a unique programming service, where a few user-defined locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number, which can serve as an entry-code, password or id number.
pic10f220/222 ds41270b-page 8 preliminary ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. preliminary ds41270b-page 9 pic10f220/222 3.0 architectural overview the high performance of the pic10f220/222 devices can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic10f220/222 devices use a harvard archi- tecture in which program and data are accessed on separate buses. this improves bandwidth over tradi- tional von neumann architectures where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12 bits wide, making it possible to have all single-word instructions. a 12-bit wide program mem- ory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execu- tion of instructions. consequently, all instructions (33) execute in a single cycle (1 s @ 4 mhz or 500 ns @ 8 mhz) except for program branches. the table below lists program memory (flash) and data memory (ram) for the pic10f220/222 devices. the pic10f220/222 devices can directly or indirectly address its register files and data memory. all special function registers (sfr), including the pc, are mapped in the data memory. the pic10f220/222 devices have a highly orthogonal (symmetrical) instruc- tion set that makes it possible to carry out any opera- tion, on any register, using any addressing mode. this symmetrical nature and lack of ?special optimal situa- tions? make programming with the pic10f220/222 devices simple, yet efficient. in addition, the learning curve is reduced significantly. the pic10f220/222 devices contain an 8-bit alu and working register. the alu is a general purpose arith- metic unit. it performs arithmetic and boolean functions between data in the working register and any register file. the alu is 8-bits wide and capable of addition, sub- traction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two?s comple- ment in nature. in two-operand instructions, one oper- and is typically the w (working) register. the other operand is either a file register or an immediate constant. in single operand instructions, the operand is either the w register or a file register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc) and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respec- tively, in subtraction. see the subwf and addwf instructions for examples. a simplified block diagram is shown in figure 3-1 with the corresponding device pins described in table 3-1. device memory program data pic10f220 256 x 12 16 x 8 pic10f222 512 x 12 23 x 8
pic10f220/222 ds41270b-page 10 preliminary ? 2006 microchip technology inc. figure 3-1: block diagram table 3-1: pinout description name function input type output type description gp0/an0/icspdat gp0 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. an0 an ? analog input icspdat st cmos in-circuit programming data gp1/an1/icspclk gp1 ttl cmos bidirectional i/o pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. an1 an ? analog input icspclk st ? in-circuit programming clock gp2/t0cki/fosc4 gp2 ttl cmos bidirectional i/o pin t0cki st ? clock input to tmr0 f osc 4 ? cmos oscillator/4 output gp3/mclr /v pp gp3 ttl ? input pin. can be software programmed for internal weak pull-up and wake-up from sleep on pin change. mclr st ? master clear (reset). when configured as mclr , this pin is an active-low reset to the device. voltage on mclr /v pp must not exceed v dd during normal device operation or the device will enter programming mode. weak pull-up always on if configured as mclr . v pp hv ? programming voltage input v dd v dd p ? positive supply for logic and i/o pins v ss v ss p ? ground reference for logic and i/o pins legend: i = input, o = output, i/o = input/output, p = power, ? = not used, ttl = ttl input, st = schmitt trigger input, an = analog input flash program memory 9-10 data bus 8 12 program bus instruction reg program counter ram file registers direct addr 5 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg device reset power-on reset watchdog timer instruction decode & control timing generation mclr v dd , v ss timer0 gpio 8 8 gp3/mclr/v pp gp2/t0cki/f osc 4 gp1/an1/icspclk gp0/an0/icspdat 5-7 3 stack1 stack2 23 or 16 internal rc clock 512 x 12 or bytes timer 256 x 12 adc an1 an0 absolute voltage reference
? 2006 microchip technology inc. preliminary ds41270b-page 11 pic10f220/222 3.1 clocking scheme/instruction cycle the clock is internally divided by four to generate four non-overlapping quadrature clocks, namely q1, q2, q3 and q4. internally, the pc is incremented every q1, and the instruction is fetched from program memory and latched into the instruction register (ir) in q4. it is decoded and executed during q1 through q4. the clocks and instruction execution flow is shown in figure 3-2 and example 3-1. 3.2 instruction flow/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the pc to change (e.g., goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the pc incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register in cycle q1. this instruc- tion is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (oper- and read) and written during q4 (destination write). figure 3-2: clock /instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc pc pc + 1 pc + 2 fetch inst (pc) execute inst (pc - 1) fetch inst (pc + 1) execute inst (pc) fetch inst (pc + 2) execute inst (pc + 1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles, since the fetch instruction is ?flushed? from the pipeline, while the new instruction is being fetched and then executed. 1. movlw 03h fetch 1 execute 1 2. movwf gpio fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf gpio, bit1 fetch 4 flush fetch sub_1 execute sub_1
pic10f220/222 ds41270b-page 12 preliminary ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. preliminary ds41270b-page 13 pic10f220/222 4.0 memory organization the pic10f220/222 memories are organized into pro- gram memory and data memory. data memory banks are accessed using the file select register (fsr). 4.1 program memory organization for the pic10f220 the pic10f220 devices have a 9-bit program counter (pc) capable of addressing a 512 x 12 program memory space. only the first 256 x 12 (0000h-00ffh) for the pic10f220 are physically implemented (see figure 4-1). accessing a location above these boundaries will cause a wrap-around within the first 256 x 12 space (pic10f220). the effective reset vector is at 0000h, (see figure 4-1). location 00ffh (pic10f220) contains the internal clock oscillator calibration value. this value should never be overwritten. figure 4-1: program memory map and stack for the pic10f220 4.2 program memory organization for the pic10f222 the pic10f222 devices have a 10-bit program counter (pc) capable of addressing a 1024 x 12 program memory space. only the first 512 x 12 (0000h-01ffh) for the mem- high are physically implemented (see figure 4-2). accessing a location above these boundaries will cause a wrap-around within the first 512 x 12 space (pic10f222). the effective reset vector is at 0000h, (see figure 4-2). location 01ffh (pic10f222) con- tains the internal clock oscillator calibration value. this value should never be overwritten. figure 4-2: program memory map and stack for the pic10f222 call, retlw pc<7:0> stack level 1 stack level 2 user memory space 9 0000h 01ffh on-chip program memory reset vector (1) note 1: address 0000h becomes the effective reset vector. location 00ffh contains the movlw xx internal oscillator calibration value. 256 word 00ffh 0100h <8:0> call, retlw pc<8:0> stack level 1 stack level 2 user memory space 10 0000h 02ffh reset vector (1) note 1: address 0000h becomes the effective reset vector. location 01ffh contains the movlw xx internal oscillator calibration value. 512 words 01ffh 0200h on-chip program memory <9:0>
pic10f220/222 ds41270b-page 14 preliminary ? 2006 microchip technology inc. 4.3 data memory organization data memory is composed of registers or bytes of ram. therefore, data memory for a device is specified by its register file. the register file is divided into two functional groups: special function registers (sfr) and general purpose registers (gpr). the special function registers include the tmr0 reg- ister, the program counter (pcl), the status register, the i/o register (gpio) and the file select register (fsr). in addition, special function registers are used to control the i/o port configuration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic10f220, the register file is composed of 9 special function registers and 16 general purpose registers (figure 4-3, figure 4-4). for the pic10f222, the register file is composed of 9 special function registers and 23 general purpose registers (figure 4-4). 4.3.1 general purpose register file the general purpose register file is accessed, either directly or indirectly, through the file select register (fsr). see section 4.9 ?indirect data addressing; indf and fsr registers? . figure 4-3: pic10f220 register file map figure 4-4: pic10f222 register file map 4.3.2 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral functions to control the operation of the device (table 4-1). the special function registers can be classified into two sets. the special function registers associated with the ?core? functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. file address 00h 01h 02h 03h 04h 05h 06h 07h 10h indf (1) tmr0 pcl status fsr osccal gpio general purpose registers note 1: not a physical register. see section 4.9 ?indirect data addressing; indf and fsr registers? . 2: unimplemented, read as 00h. 08h adcon0 0fh 1fh unimplemented (2) adres 09h file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr osccal gpio note 1: not a physical register. see section 4.9 ?indirect data addressing; indf and fsr registers? . 08h adres 09h adcon0 general purpose registers
? 2006 microchip technology inc. preliminary ds41270b-page 15 pic10f220/222 table 4-1: special function register (sfr) summary 4.4 status register this register contains the arithmetic status of the alu, the reset status and the page preselect bit. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). therefore, it is recommended that only bcf , bsf and movwf instructions be used to alter the status regis- ter. these instructions do not affect the z, dc or c bits from the status register. for other instructions, which do affect status bits, see instruction set summary. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset (2) page # 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx 20 01h tmr0 8-bit real-time clock/counter xxxx xxxx 25 02h pcl (1) low order 8 bits of pc 1111 1111 19 03h status gpwuf ? ?to pd zdcc 0--1 1xxx (3) 15 04h fsr indirect data memory address pointer 111x xxxx 20 05h osccal cal6 cal5 cal4 cal3 cal2 cal1 cal0 fosc4 1111 1110 18 06h gpio ? ? ? ? gp3 gp2 gp1 gp0 ---- xxxx 21 07h adcon0 ans1 ans0 ? ? chs1 chs0 go/done adon 11-- 1100 30 08h adres result of analog-to-digital conversion xxxx xxxx 31 n/a trisgpio ? ? ? ? i/o control register ---- 1111 23 n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 17 legend: ? = unimplemented, read as ? 0 ?, x = unknown, u = unchanged, q = value depends on condition. note 1: the upper byte of the program counter is not directly accessible. see section 4.7 ?program counter? for an explanation of how to access these bits. 2: other (non power-up) resets in clude external reset through mclr , watchdog timer and wake-up on pin change reset. 3: see table 8-1 for other reset specific values.
pic10f220/222 ds41270b-page 16 preliminary ? 2006 microchip technology inc. register 4-1: status register: (address: 03h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x gpwuf ? ?to pd zdcc bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gpwuf: gpio reset bit 1 = reset due to wake-up from sleep on pin change 0 = after power-up or other reset bit 6 reserved: do not use. use of this bit may affect upward compatibility with future products. bit 5 reserved: do not use. use of this bit may affect upward compatibility with future products. bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/borrow bit (for addwf and subwf instructions) addwf : 1 = a carry to the 4th low-order bit of the result occurred 0 = a carry to the 4th low-order bit of the result did not occur subwf : 1 = a borrow from the 4th low-order bit of the result did not occur 0 = a borrow from the 4th low-order bit of the result occurred bit 0 c: carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf : subwf : rrf or rlf : 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb, respectively 0 = a carry did not occur 0 = a borrow occurred
? 2006 microchip technology inc. preliminary ds41270b-page 17 pic10f220/222 4.5 option register the option register is a 8-bit wide, write-only register, which contains various control bits to configure the timer0/wdt prescaler and timer0. the option register is not memory mapped and is therefore only addressable by executing the option instruction, the contents of the w register will be trans- ferred to the option register. a reset sets the option<7:0> bits. note: if tris bit is set to ? 0 ?, the wake-up on change and pull-up functions are disabled for that pin (i.e., note that tris overrides option control of gppu and gpwu) . note: if the t0cs bit is set to ? 1 ?, it will override the tris function on the t0cki pin. register 4-2: option register: (pic10f22x) w-1 w-1 w-1 w-1 w-1 w-1 w-1 w-1 gpwu gppu t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gpwu : enable wake-up on pin change bit (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 6 gppu : enable weak pull-ups bit (gp0, gp1, gp3) 1 = disabled 0 = enabled bit 5 t0cs: timer0 clock source select bit 1 = transition on t0cki pin (overrides tris on the t0cki pin) 0 = transition on internal instruction cycle clock, f osc /4 bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on the t0cki pin 0 = increment on low-to-high transition on the t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0 ps<2:0>: prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
pic10f220/222 ds41270b-page 18 preliminary ? 2006 microchip technology inc. 4.6 osccal register the oscillator calibration (osccal) register is used to calibrate the internal precision 4/8 mhz oscillator. it contains seven bits for calibration . after you move in the calibration constant, do not change the value. see section 8.2.2 ?internal 4/ 8 mhz oscillator? . note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. register 4-3: osccal register: (address: 05h) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-0 cal6 cal5 cal4 cal3 cal2 cal1 cal0 fosc4 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 cal<6:0>: oscillator calibration bits 0111111 = maximum frequency ? ? ? 0000001 0000000 = center frequency 1111111 ? ? ? 1000000 = minimum frequency bit 0 fosc4: intosc/4 output enable bit (1) 1 = intosc/4 output onto gp2 0 = gp2/t0cki applied to gp2 note 1: overrides gp2/t0cki control registers when enabled.
? 2006 microchip technology inc. preliminary ds41270b-page 19 pic10f220/222 4.7 program counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the pc latch (pcl) is mapped to pc<7:0>. for a call instruction or any instruction where the pcl is the destination, bits 7:0 of the pc again are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-5). instructions where the pcl is the destination or modify pcl instructions, include movwf pc , addwf pc and bsf pc , 5. figure 4-5: loading of pc branch instructions 4.7.1 effects of reset the pc is set upon a reset, which means that the pc addresses the last location in program memory (i.e., the oscillator calibration instruction). after executing movlw xx , the pc will roll over to location 0000h and begin executing user code. 4.8 stack the pic10f220 device has a 2-deep, 8-bit wide hardware push/pop stack. the pic10f222 device has a 2-deep, 9-bit wide hardware push/pop stack. a call instruction will push the current value of stack 1 into stack 2 and then push the current pc value, incremented by one, into stack level 1. if more than two sequential call ?s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the pc and then copy stack level 2 contents into level 1. if more than two sequential retlw ?s are exe- cuted, the stack will be filled with the address previously stored in level 2. note: because pc<8> is cleared in the call instruction or any modify pcl instruction, all subroutine calls or computed jumps are limited to the first 256 locations of any program memory page (512 words long). pc 87 0 pcl instruction word goto instruction call or modify pcl instruction pc 87 0 pcl instruction word reset to ? 0 ? note 1: the w register will be loaded with the lit- eral value specified in the instruction. this is particularly useful for the implementa- tion of data look-up tables within the program memory. 2: there are no status bits to indicate stack overflows or stack underflow conditions. 3: there are no instructions mnemonics called push or pop. these are actions that occur from the execution of the call and retlw instructions.
pic10f220/222 ds41270b-page 20 preliminary ? 2006 microchip technology inc. 4.9 indirect data addressing; indf and fsr registers the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. 4.9.1 indirect addressing ? register file 09 contains the value 10h ? register file 0a contains the value 0ah ? load the value 09 into the fsr register ? a read of the indf register will return the value of 10h ? increment the value of the fsr register by one (fsr = 0a) ? a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0 ) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-1. example 4-1: how to clear ram using indirect addressing the fsr is a 5-bit wide register. it is used in conjunc- tion with the indf register to indirectly address the data memory area. the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. figure 4-6: direct/indirect addressing note: do not use banking. fsr <7:5> are unimplemented and read as ? 1 ?s. movlw 0x10 ;initialize po inter movwf fsr ;to ram next clrf indf ;clear indf ;register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue : note 1: for register map detail, see section 4.3 ?data memory organization? . location select location select indirect addressing direct addressing data memory (1) 0fh 10h bank 0 0 4 (fsr) 00h 1fh (opcode) 0 4
? 2006 microchip technology inc. preliminary ds41270b-page 21 pic10f220/222 5.0 i/o port as with any other register, the i/o register(s) can be written and read under program control. however, read instructions (e.g., movf gpio, w ) always read the i/o pins independent of the pin?s input/output modes. on reset, all i/o ports are defined as input (inputs are at high-impedance) since the i/o control registers are all set. 5.1 gpio gpio is an 8-bit i/o register. only the low-order 4 bits are used (gp<3:0>). bits 7 through 4 are unimple- mented and read as ? 0 ?s. please note that gp3 is an input only pin. pins gp0, gp1 and gp3 can be config- ured with weak pull-ups and also for wake-up on change. the wake-up on change and weak pull-up functions are not individually pin selectable. if gp3/ mclr is configured as mclr , a weak pull-up can be enabled via the configuration word. configuring gp3 as mclr disables the wake-up on change function for this pin. 5.2 tris registers the output driver control register is loaded with the contents of the w register by executing the tris f instruction. a ? 1 ? from a tris register bit puts the corre- sponding output driver in a high-impedance mode. a ? 0 ? puts the contents of the output data latch on the selected pins, enabling the output buffer. the excep- tions are gp3, which is input only, and the gp2/t0cki/ fosc4 pin, which may be controlled by various registers. see table 5-1. the tris registers are ?write-only? and are set (output drivers disabled) upon reset. 5.3 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-5. all port pins, except gp3, which is input only, may be used for both input and output operations. for input operations, these ports are non-latching. any input must be present until read by an input instruction (e.g., movf gpio, w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corresponding direction control bit in tris must be cleared (= 0 ). for use as an input, the corresponding tris bit must be set. any i/o pin (except gp3) can be programmed individually as input or output. figure 5-1: equivalent circuit for a single i/o pin table 5-1: order of precedence for pin functions table 5-2: requirements to make pins available in digital mode note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. data bus q d q ck q d q ck p n wr port tris ?f? data tris rd port v ss v dd i/o pin w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . 2: see table 3-1 for buffer type. v ss v dd (2) (1) priority gp0 gp1 gp2 gp3 1 an0 an1 fosc4 m clr 2 tris gpio tris gpio t0cki ? 3 ? ? tris gpio ? bit gp0 gp1 gp2 gp3 fosc4 ? ? 0 ? t0cs ? ? 0 ? ans1 ? 0 ? ? ans0 0 ? ? ? mclre ? ? ? 0 legend: ? = condition of bit will have no effect on the setting of the pin to digital mode.
pic10f220/222 ds41270b-page 22 preliminary ? 2006 microchip technology inc. figure 5-2: block diagram of gp0 and gp1 figure 5-3: block diagram of gp2 figure 5-4: block diagram of gp3 data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . d ck q mis-match gppu adc i/o pin (1 ) analog enable data bus q d q ck q d q ck wr port tris ?f? data tris rd port w reg latch latch reset note 1: i/o pins have protection diodes to v dd and v ss . t0cki i/o pin (1) t0cs f osc 4 osccal<0> data bus rd port note 1: gp3/mclr pin has a protection diode to v ss only. gppu d ck q mis-match mclre reset i/o pin (1 )
? 2006 microchip technology inc. preliminary ds41270b-page 23 pic10f220/222 table 5-3: summary of port registers 5.4 i/o programming considerations 5.4.1 bidirectional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit 2 of gpio will cause all eight bits of gpio to be read into the cpu, bit 2 to be set and the gpio value to be written to the output latches. if another bit of gpio is used as a bidirectional i/o pin (say bit 0) and it is defined as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit 0 is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (?wired-or?, ?wired-and?). the resulting high output currents may damage the chip. example 5-1: i/o port read-modify- write instructions 5.4.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-5). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction causes that file to be read into the cpu. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-5: successive i/o operation address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a trisgpio ? ? ? ? i/o control registers ---- 1111 ---- 1111 n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 03h status gpwuf ? ? to pd z dc c 0001 1xxx q00q quuu (1) 06h gpio ? ? ? ? gp3 gp2 gp1 gp0 ---- xxxx ---- uuuu legend: shaded cells not used by port registers, read as ? 0 ?, ? = unimplemented, read as ? 0 ?, x = unknown, u = unchanged, q = depends on condition. note 1: if reset was due to wake-up on pin change, then bit 7 = 1 . all other resets will cause bit 7 = 0 . ;initial gpio settings ;gpio<3:2> inputs ;gpio<1:0> outputs ; ; gpio latch gpio pins ; ---------- ---------- bcf gpio, 1 ;---- pp01 ---- pp11 bcf gpio, 0 ;---- pp10 ---- pp11 movlw 007h; tris gpio ;---- pp10 ---- pp11 ; note: the user may have expected the pin values t o be ---- pp00 . the second bcf caused gp 1 to be latched as the pin value (high). pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched gp<2:0> movwf gpio nop port pin sampled here nop movf gpio , w instruction executed movwf gpio (write to gpio) nop movf gpio,w this example shows a write to gpio followed by a read from gpio. data setup time = (0.25 t cy ? t pd ) where: t cy = instruction cycle t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read gpio) port pin written here
pic10f220/222 ds41270b-page 24 preliminary ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. preliminary ds41270b-page 25 pic10f220/222 6.0 tmr0 module and tmr0 register the timer0 module has the following features: ? 8-bit timer/counter register, tmr0 ? readable and writable ? 8-bit software programmable prescaler ? internal or external clock select: - edge select for external clock figure 6-1 is a simplified block diagram of the timer0 module. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-2 and figure 6-3). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the t0se bit (option<4>) determines the source edge. clearing the t0se bit selects the rising edge. restric- tions on the external clock input are discussed in detail in section 6.1 ?using timer0 with an external clock? . the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4, 1:256 are selectable. section 6.2 ?prescaler? details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. figure 6-1: timer0 block diagram figure 6-2: timer0 timing: internal clock/no prescale note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-5). 0 1 1 0 t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg ps out (2 t cy delay) ps out data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync t0se gp2/t0cki pin pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 t0 + 2 nt0 nt0 + 1 nt0 + 2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter)
pic10f220/222 ds41270b-page 26 preliminary ? 2006 microchip technology inc. figure 6-3: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 6.1 using timer0 with an external clock when an external clock input is used for timer0, it must meet certain requirements. the external clock require- ment is due to internal phase clock (t osc ) synchroniza- tion. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-4). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 2tt0h) and low for at least 2t osc (and a small rc delay of 2tt0h). refer to the electrical specification of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler, so that the prescaler output is symmetrical. for the external clock to meet the sampling require- ment, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 4tt0h) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of tt0h. refer to parameters 40, 41 and 42 in the electrical specification of the desired device. address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets 01h tmr0 timer0 ? 8-bit real-time clock/counter xxxx xxxx uuuu uuuu n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 n/a trisgpio (1) ? ? ? ? i/o control register ---- 1111 ---- 1111 legend: shaded cells not used by timer0, ? = unimplemented, x = unknown, u = unchanged. note 1: the tris of the t0cki pin is overridden when t0cs = 1 pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetch timer0 pc pc + 1 pc + 2 pc + 3 pc + 4 pc + 6 t0 t0 + 1 nt0 nt0 + 1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc + 5 pc (program counter)
? 2006 microchip technology inc. preliminary ds41270b-page 27 pic10f220/222 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 mod- ule is actually incremented. figure 6-4 shows the delay from the external clock edge to the timer incrementing. figure 6-4: timer0 timing with external clock 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module or as a postscaler for the watchdog timer (wdt), respectively (see section 8.6 ?watch- dog timer (wdt)? ). for simplicity, this counter is being referred to as ?prescaler? throughout this data sheet. the psa and ps<2:0> bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all ? 0 ?s. increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses samplin g external clock/prescaler output after sampling (3) prescaler output (2) (1) note 1: delay from clock input change to timer0 increment is 3t osc to 7t osc . (duration of q = t osc ). therefore, the error in measuring the interval between two edges on timer0 input = 4t osc max. 2: external clock if no prescaler selected; prescaler output otherwise. 3: the arrows indicate the points in time where sampling occurs. note: the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt and vice-versa.
pic10f220/222 ds41270b-page 28 preliminary ? 2006 microchip technology inc. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on-the-fly? during pro- gram execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 wdt) to change prescaler from the wdt to the timer0 module, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 6-2: changing prescaler (wdt timer0) figure 6-5: block diagram of the timer0/wdt prescaler clrwdt ;clear wdt clrf tmr0 ;clear tmr0 & prescaler movlw ?00xx1111?b ;these 3 lines (5, 6, 7) option ;are required only if ;desired clrwdt ;ps<2:0> are 000 or 001 movlw ?00xx1xxx?b ;set postscaler to option ;desired wdt rate clrwdt ;clear wdt and ;prescaler movlw ?xxxx0xxx? ;select tmr0, new ;prescale value and ;clock source option t cy (= f osc /4) sync 2 cycles tmr0 reg 8-bit prescaler 8-to-1 mux m mux watchdog timer psa (1) 0 1 0 1 wdt time-out ps<2:0> (1) 8 psa (1) wdt enable bit 0 1 0 1 data bus 8 psa (1) t0cs (1) m u x m u x u x t0se (1) gp2/t0cki (2) pin note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register. 2: t0cki is shared with pin gp2 on the pic10f220/222.
? 2006 microchip technology inc. preliminary ds41270b-page 29 pic10f220/222 7.0 analog-to-digital (a/d) converter the a/d converter allows conversion of an analog signal into an 8-bit digital signal. 7.1 clock divisors the a/d converter has a single clock source setting, intosc/4. the a/d converter requires 13 t ad periods to complete a conversion. the divisor values do not affect the number of t ad periods required to perform a conversion. the divisor values determine the length of the t ad period. 7.2 voltage reference due to the nature of the design, there is no external voltage reference allowed for the a/d converter. the a/d converter reference voltage will always be v dd . 7.3 analog mode selection the ans<1:0> bits are used to configure pins for ana- log input. upon any reset ans<1:0> defaults to 11. this configures pins an0 and an1 as analog inputs. pins configured as analog inputs are not available for digital output. users should not change the ans bits while a conversion is in process. ans bits are active regardless of the condition of adon. 7.4 a/d converter channel selection the chs bits are used to select the analog channel to be sampled by the a/d converter. the chs bits should not be changed during a conversion. to acquire an analog signal, the chs selection must match one of the pin(s) selected by the ans bits. the internal absolute voltage reference can be selected regardless of the condition of the ans bits. all channel selection information will be lost when the device enters sleep. 7.5 the go/done bit the go/done bit is used to determine the status of a conversion, to start a conversion and to manually halt a conversion in process. setting the go/done bit starts a conversion. when the conversion is complete, the a/ d converter module clears the go/done bit. a con- version can be terminated by manually clearing the go/done bit while a conversion is in process. manual termination of a conversion may result in a partially converted result in adres. the go/done bit is cleared when the device enters sleep, stopping the current conversion. the a/d con- verter does not have a dedicated oscillator, it runs off of the system clock. the go/done bit cannot be set when adon is clear. 7.6 sleep this a/d converter does not have a dedicated a/d converter clock and therefore no conversion in sleep is possible. if a conversion is underway and a sleep command is executed, the go/done and adon bit will be cleared. this will stop any conversion in process and power-down the a/d converter module to con- serve power. due to the nature of the conversion pro- cess, the adres may contain a partial conversion. at least 1 bit must have been converted prior to sleep to have partial conversion data in adres. the chs bits are reset to their default condition and chs<1:0> = 11 . for accurate conversions, t ad must meet the following: ? 500 ns < t ad < 50 s ?t ad = 1/(f osc /divisor) table 7-1: effects of sleep and wake on adcon0 note: due to the fixed clock divisor, a conversion will complete in 13 cpu instruction cycles. note: the a/d converter module consumes power when the adon bit is set even when no channels are selected as analog inputs. for low-power applications, it is recommended that the adon bit be cleared when the a/d converter is not in use. ans1 ans0 chs1 chs0 go/done adon prior to sleep xxxx00 prior to sleep xxxx11 entering sleep unchanged unchanged 1100 wake 111100
pic10f220/222 ds41270b-page 30 preliminary ? 2006 microchip technology inc. 7.7 analog conversion result register the adres register contains the results of the last conversion. these results are present during the sam- pling period of the next analog conversion process. after the sampling period is over, adres is cleared (= 0 ). a ?leading one? is then right shifted into the adres to serve as an internal conversion complete bit. as each bit weight, starting with the msb, is converted, the leading one is shifted right and the converted bit is stuffed into adres. after a total of 9 right shifts of the ?leading one? have taken place, the conversion is com- plete; the ?leading one? has been shifted out and the go/done bit is cleared. if the go/done bit is cleared in software during a con- version, the conversion stops. the data in adres is the partial conversion result. this data is valid for the bit weights that have been converted. the position of the ?leading one? determines the number of bits that have been converted. the bits that were not converted before the go/done was cleared are unrecoverable. 7.8 internal absolute voltage reference the function of the internal absolute voltage refer- ence is to provide a constant voltage for conversion across the devices v dd supply range. the a/d con- verter is ratiometric with the conversion reference voltage being v dd . converting a constant voltage of 0.6v (typical) will result in a result based on the voltage applied to v dd of the device. the result of conversion of this reference across the v dd range can be approximated by: conversion result = 0.6v/(v dd /256) note: the actual value of the absolute voltage reference varies with temperature and part-to-part variation. the conversion is also susceptible to analog noise on the v dd pin and noise generated by the sink- ing or sourcing of current on the i/o pins. register 7-1: adcon0 register (address 07h) r/w-1 r/w-1 u-0 u-0 r/w-1 r/w-1 r/w-0 r/w-0 ans1 ans0 ? ? chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ans1: adc analog input pin select bit 1 = gp1/an1 configured for analog input 0 = gp1/an1 configured as digital i/o bit 6 ans0: adc analog input pin select bit (1), (2) 1 = gp0/an0 configured as an analog input 0 = gp0/an0 configured as digital i/o bit 5-4 unimplemented: read as ? 0 ? bit 3-2 chs<1:0>: adc channel select bits (3) 00 = channel 00 (gp0/an0) 01 = channel 01 (gp1/an1) 1x = 0.6v absolute voltage reference bit 1 go/done : adc conversion status bit (4) 1 = adc conversion in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc is done converting. 0 = adc conversion completed/not in progress. manually cl earing this bit while a conversion is in process terminates the current conversion. note 1: when the ans bits are set, the channel(s) selected are autom atically forced into analog mode regardless of the pin function previously defined. 2: the ans<1:0> bits are active regardless of the condition of adon 3: chs<1:0> bits default to 11 after any reset. 4: if the adon bit is clear, the go/done bit cannot be set.
? 2006 microchip technology inc. preliminary ds41270b-page 31 pic10f220/222 bit 0 adon: adc enable bit 1 = adc module is operating 0 = adc module is shut-off and consumes no power register 7-1: adcon0 register (address 07h) (continued) note 1: when the ans bits are set, the channel(s) selected are autom atically forced into analog mode regardless of the pin function previously defined. 2: the ans<1:0> bits are active regardless of the condition of adon 3: chs<1:0> bits default to 11 after any reset. 4: if the adon bit is clear, the go/done bit cannot be set. register 7-2: adres register (address 08h) r-x r-x r-x r-x r-x r-x r-x r-x adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 adres<7:0>
pic10f220/222 ds41270b-page 32 preliminary ? 2006 microchip technology inc. 7.9 a/d acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 7-1. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 7-1. the maximum recommended impedance for analog sources is 10 k . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an a/d acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 7-1 may be used. this equation assumes that 1/2 lsb error is used (256 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 7-1: acquisition time example figure 7-1: analog input model t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c () 0.05s/c () [] ++ = t c c hold r ic r ss r s ++ () ln(1/512) ? = 25 pf 1k 7k 10k ++ () ? ln(0.00196) = 2.81 = s t acq 2 s 2.81 s 50c- 25c () 0.05 s /c () [] ++ = 6.06 u s = solving for t c : therefore: temperature 50c and external impedance of 10k 5.0v v dd = assumptions: note 1: the charge holding capacitor (c hold ) is not discharged after each conversion. 2: the maximum recommended impedance for analog sources is 10 k . this is required to meet the pin leakage specification. c pin va rs anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss rss c hold = 25 pf v ss /v ref - 6v sampling switch 5v 4v 3v 2v 567891011 (k ) v dd 500 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss
? 2006 microchip technology inc. preliminary ds41270b-page 33 pic10f220/222 8.0 special features of the cpu what sets a microcontroller apart from other proces- sors are special circuits that deal with the needs of real- time applications. the pic10f220/222 microcontrol- lers have a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power-saving operating modes and offer code protection. these features are: ? reset: - power-on reset (por) - device reset timer (drt) - watchdog timer (wdt) - wake-up from sleep on pin change ? sleep ? code protection ? id locations ? in-circuit serial programming? ?clock out the pic10f220/222 devices have a watchdog timer, which can be shut off only through configuration bit wdte. it runs off of its own rc oscillator for added reli- ability. when using drt, there is an 1.125 ms (typical) delay only on v dd power-up. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through a change on input pins or through a watchdog timer time-out. 8.1 configuration bits the pic10f220/222 configuration words consist of 12 bits. configuration bits can be programmed to select various device configurations. one bit is the watchdog timer enable bit, one bit is the mclr enable bit and one bit is for code protection (see register 8-1). register 8-1: configuratio n word for pic10f220/222 (1) ? ? ? ? ? ? ? mclre cp wdte mcpu ioscfs bit 11 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 11-5 unimplemented: read as ? 0 ? bit 4 mclre: gp3/mclr pin function select bit 1 = gp3/mclr pin function is mclr 0 = gp3/mclr pin function is digital i/o, mclr internally tied to v dd bit 3 cp : code protection bit 1 = code protection off 0 = code protection on bit 2 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1 mcpu : master clear pull-up enable (2) 1 = pull-up disabled 0 = pull-up enabled bit 0 ioscfs: internal oscillator frequency select 1 = 8 mhz 0 = 4 mhz note 1: refer to the ? pic10f220/222 memory programming specification ? (ds41266), to determine how to access the configuration word. the configuration word is not user addressable during device operation. 2: mclre must be a ? 1 ? to enable this selection.
pic10f220/222 ds41270b-page 34 preliminary ? 2006 microchip technology inc. 8.2 oscillator configurations 8.2.1 oscillator types the pic10f220/222 devices are offered with internal oscillator mode only. ? intosc: internal 4/8 mhz oscillator 8.2.2 internal 4/8 mhz oscillator the internal oscillator provides a 4/8 mhz (nominal) system clock (see section 10.0 ?electrical charac- teristics? for information on variation over voltage and temperature). in addition, a calibration instruction is programmed into the last address of memory, which contains the calibra- tion value for the internal oscillator. this location is always uncode protected, regardless of the code-pro- tect settings. this value is programmed as a movlw xx instruction where xx is the calibration value and is placed at the reset vector. this will load the w register with the calibration value upon reset and the pc will then roll over to the users program at address 0x000. the user then has the option of writing the value to the osccal register (05h) or ignoring it. osccal, when written to with the calibration value, will ?trim? the internal oscillator to remove process variation from the oscillator frequency. 8.3 reset the device differentiates between various kinds of reset: ? power-on reset (por) ?mclr reset during normal operation ?mclr reset during sleep ? wdt time-out reset during normal operation ? wdt time-out reset during sleep ? wake-up from sleep on pin change some registers are not reset in any way, they are unknown on por and unchanged in any other reset. most other registers are reset to ?reset state? on power-on reset (por), mclr , wdt or wake-up on pin change reset during normal operation. they are not affected by a wdt reset during sleep or mclr reset during sleep, since these resets are viewed as resumption of normal operation. the exceptions to this are to , pd and gpwuf bits. they are set or cleared differently in different reset situations. these bits are used in software to determine the nature of reset. see table 8-1 for a full description of reset states of all registers. table 8-1: reset conditions for registers ? pic10f220/222 note: erasing the device will also erase the pre- programmed internal calibration value for the internal oscillator. the calibration value must be read prior to erasing the part so it can be reprogrammed correctly later. register address power-on reset mclr reset, wdt time-out, wake-up on pin change, w? qqqq qqqu (1) qqqq qqqu (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pc 02h 1111 1111 1111 1111 status 03h 0--1 1xxx q00q quuu fsr 04h 111x xxxx 111u uuuu osccal 05h 1111 1110 uuuu uuuu gpio 06h ---- xxxx ---- uuuu adcon0 07h 11-- 1100 11-- 1100 adres 08h xxxx xxxx uuuu uuuu option ? 1111 1111 1111 1111 tris ? ---- 1111 ---- 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?, q = value depends on condition. note 1: bits <7:2> of w register contain os cillator calibration values due to movlw xx instruction at top of memory.
? 2006 microchip technology inc. preliminary ds41270b-page 35 pic10f220/222 table 8-2: reset condition for special registers 8.3.1 mclr enable this configuration bit, when unprogrammed (left in the ? 1 ? state), enables the external mclr function. when programmed, the mclr function is tied to the internal v dd and the pin is assigned to be a i/o. see figure 8-1. figure 8-1: mclr select 8.4 power-on reset (por) the pic10f220/222 devices incorporate an on-chip power-on reset (por) circuitry, which provides an internal chip reset for most power-up situations. the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper oper- ation. to take advantage of the internal por, program the gp3/mclr /v pp pin as mclr and tie through a resistor to v dd , or program the pin as gp3. an internal weak pull-up resistor is implemented using a transistor (refer to table 10-2 for the pull-up resistor ranges). this will eliminate external rc components usually needed to create a power-on reset. a maximum rise time for v dd is specified. see section 10.0 ?electrical char- acteristics? for details. when the devices start normal operation (exit the reset condition), device operating parameters (volt- age, frequency, temperature,...) must be met to ensure operation. if these conditions are not met, the devices must be held in reset until the operating parameters are met. a simplified block diagram of the on-chip power-on reset circuit is shown in figure 8-2. the power-on reset circuit and the device reset timer (see section 8.5 ?device reset timer (drt)? ) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 1.125 ms, it will reset the reset latch and thus end the on-chip reset signal. a power-up example where mclr is held low is shown in figure 8-3. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 8-4, the on-chip power-on reset feature is being used (mclr and v dd are tied together or the pin is programmed to be gp3). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 8-5 depicts a problem situation where v dd rises too slowly. the time between when the drt senses that mclr is high and when mclr and v dd actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip may not function correctly. for such situations, we recommend that external rc circuits be used to achieve longer por delay times (figure 8-4). for additional information, refer to application notes an522, ?power-up considerations? (ds00522) and an607, ?power-up trouble shooting? (ds00607). status addr: 03h pcl addr: 02h power-on reset 0--1 1xxx 1111 1111 mclr reset during normal operation 0--u uuuu 1111 1111 mclr reset during sleep 0--1 0uuu 1111 1111 wdt reset during sleep 0--0 0uuu 1111 1111 wdt reset normal operation 0--0 uuuu 1111 1111 wake-up from sleep on pin change 1--1 0uuu 1111 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?. gp3/mclr /v pp mclre internal mclr gpwu weak pull-up note: when the devices start normal operation (exit the reset condition), device operat- ing parameters (voltage, frequency, tem- perature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met.
pic10f220/222 ds41270b-page 36 preliminary ? 2006 microchip technology inc. figure 8-2: simplified block diagram of on-chip reset circuit figure 8-3: time-out sequence on power-up (mclr pulled low) figure 8-4: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time sq r q v dd gp3/mclr /v pp power-up detect por (power-on wdt reset chip rese t mclre wake-up on pin change reset start-up timer wdt time-out pin change sleep mclr reset 1.125 ms reset) v dd mclr internal por drt time-out internal reset tdrt v dd mclr internal por drt time-out internal reset tdrt
? 2006 microchip technology inc. preliminary ds41270b-page 37 pic10f220/222 figure 8-5: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset tdrt v1 note: when v dd rises slowly, the t drt time-out expires long before v dd has reached its final value. in this example, the chip will reset properly if, and only if, v1 v dd min.
pic10f220/222 ds41270b-page 38 preliminary ? 2006 microchip technology inc. 8.5 device reset timer (drt) on the pic10f220/222 devices, the drt runs any time the device is powered up. the drt operates on an internal oscillator. the pro- cessor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min. and for the oscillator to stabilize. the on-chip drt keeps the devices in a reset condi- tion for approximately 1.125 ms after mclr has reached a logic high (v ih mclr ) level. programming gp3/mclr /v pp as mclr and using an external rc network connected to the mclr input is not required in most cases. this allows savings in cost-sensitive and/ or space restricted applications, as well as allowing the use of the gp3/mclr /v pp pin as a general purpose input. the device reset time delays will vary from chip-to- chip due to v dd , temperature and process variation. see ac parameters for details. reset sources are por, mclr , wdt time-out and wake-up on pin change. see section 8.9.2 ?wake-up from sleep?, notes 1, 2 and 3 . table 8-3: drt (device reset timer period) 8.6 watchdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator, which does not require any external components. this rc oscillator is separate from the internal 4/8 mhz oscillator. this means that the wdt will run even if the main processor clock has been stopped, for example, by execution of a sleep instruc- tion. during normal operation or sleep, a wdt reset or wake-up reset, generates a device reset. the to bit (status<4>) will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by program- ming the configuration wdte as a ? 0 ? (see section 8.1 ?configuration bits? ). refer to the pic10f220/222 programming specification to determine how to access the configuration word. 8.6.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writ- ing to the option register. thus, a time-out period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to-part process variations (see dc specs). under worst-case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 8.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset. oscillator por reset subsequent resets intosc 1.125 ms (typical) 10 s (typical)
? 2006 microchip technology inc. preliminary ds41270b-page 39 pic10f220/222 figure 8-6: watchdog timer block diagram table 8-4: summary of registers associated with the watchdog timer 8.7 time-out sequence, power-down and wake-up from sleep status bits (to /pd /gpwuf/cwuf) the to , pd and gpwuf bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr, watchdog timer (wdt) reset or wake-up on pin change. table 8-5: to /pd /gpwuf status after reset address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on all other resets n/a option gpwu gppu t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 legend: shaded boxes = not used by watchdog timer, ? = unimplemented, read as ? 0 ?, u = unchanged. (figure 6-5) postscaler note 1: t0cs, t0se, psa, ps<2:0> are bits in the option register. wdt time-out watchdog timer from timer0 clock source wdt enable configuration bit psa postscaler 8-to-1 mux ps<2:0> (figure 6-4) to ti me r 0 0 1 m u x 1 0 psa mux 3 gpwuf to pd reset caused by 000 wdt wake-up from sleep 00u wdt time-out (not from sleep) 010 mclr wake-up from sleep 011 power-up 0uu mclr not during sleep 110 wake-up from sleep on pin change legend: u = unchanged, x = unknown, ? = unimplemented bit, read as ? 0 ?, q = value depends on condition. note 1: the to , pd and gpwuf bits maintain their status ( u ) until a reset occurs. a low-pulse on the mclr input does not change the to , pd or gpwuf status bits.
pic10f220/222 ds41270b-page 40 preliminary ? 2006 microchip technology inc. 8.8 reset on brown-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic10f220/222 devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in figure 8-7 and figure 8-8. figure 8-7: brown-out protection circuit 1 figure 8-8: brown-out protection circuit 2 figure 8-9: brown-out protection circuit 3 8.9 power-down mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 8.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the to bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low or high-impedance). for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the gp3/ mclr /v pp pin must be at a logic high level if mclr is enabled. note 1: this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). 2: pin must be configured as mclr . 33k 10k 40k (1) v dd mclr (2) pic10f22x v dd q1 note 1: this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: 2: pin must be configured as mclr . v dd ? r1 r1 + r2 = 0.7v r2 40k (1) v dd mclr (2) pic10f22x r1 q1 v dd note: a reset generated by a wdt time-out does not drive the mclr pin low. note 1: this brown-out protection circuit employs microchip technology?s mcp809 micro- controller supervisor. there are 7 different trip point selections to accommodate 5v to 3v systems. 2: pin must be configured as mclr . mclr (2) pic10f22x v dd v dd v ss rst mcp809 v dd bypass capacitor
? 2006 microchip technology inc. preliminary ds41270b-page 41 pic10f220/222 8.9.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on gp3/mclr /v pp pin, when configured as mclr . 2. a watchdog timer time-out reset (if wdt was enabled). 3. a change on input pin gp0, gp1 or gp3 when wake-up on change is enabled. these events cause a device reset. the to , pd gpwuf bits can be used to determine the cause of a device reset. the to bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the gpwuf bit indicates a change in state while in sleep at pins gp0, gp1 or gp3 (since the last file or bit operation on gp port). 8.10 program verification/code protection if the code protection bit has not been programmed, the on-chip program memory can be read out for verification purposes. the first 64 locations and the last location (reset vector) can be read, regardless of the code protection bit setting. 8.11 id locations four memory locations are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. use only the lower 4 bits of the id locations and always program the upper 8 bits as ? 1 ?s. 8.12 in-circuit serial programming? the pic10f220/222 microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware, or a custom firmware, to be programmed. the devices are placed into a program/verify mode by holding the gp1 and gp0 pins low while raising the mclr (v pp ) pin from v il to v ihh (see programming specification). gp1 becomes the programming clock and gp0 becomes the programming data. both gp1 and gp0 are schmitt trigger inputs in this mode. after reset, a 6-bit command is then supplied to the device. depending on the command, 16 bits of program data are then supplied to or from the device, depending if the command was a load or a read. for complete details of serial programming, please refer to the pic10f220/222 programming specifications. a typical in-circuit serial programming connection is shown in figure 8-10. figure 8-10: typical in-circuit serial programming connection caution: right before entering sleep, read the input pins. when in sleep, wake up occurs when the values at the pins change from the state they were in at the last reading. if a wake-up on change occurs and the pins are not read before re-entering sleep, a wake-up will occur immediately even if no pins change while in sleep mode. note: the wdt is cleared when the device wakes from sleep, regardless of the wake- up source. external connector signals to n o r m a l connections to n o r m a l connections pic10f22x v dd v ss mclr /v pp gp1 gp0 +5v 0v v pp clk data i/o v dd
pic10f220/222 ds41270b-page 42 preliminary ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. preliminary ds41270b-page 43 pic10f220/222 9.0 instruction set summary the pic16 instruction set is highly orthogonal and is comprised of three basic categories. ? byte-oriented operations ? bit-oriented operations ? literal and control operations each pic16 instruction is a 12-bit word divided into an opcode , which specifies the instruction type, and one or more operands which further specify the operation of the instruction. the formats for each of the catego- ries is presented in figure 9-1, while the various opcode fields are summarized in table 9-1. for byte-oriented instructions, ?f? represents a file reg- ister designator and ?d? represents a destination desig- nator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator which selects the number of the bit affected by the operation, while ?f? represents the number of the file in which the bit is located. for literal and control operations, ?k? represents an 8 or 9-bit constant or literal value. table 9-1: opcode field descriptions all instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. figure 9-1 shows the three general formats that the instructions can have. all examples in the figure use the following format to represent a hexadecimal number: ?0xhhh? where ? h ? signifies a hexadecimal digit. figure 9-1: general format for instructions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ) the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in file register ? f ?) default is d = 1 label label name tos top-of-stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the specified register file location [ ] options ( ) contents assigned to < > register bit field in the set of italics user defined term (font is courier) byte-oriented file register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit file register address bit-oriented file register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit address f = 5-bit file register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations ? goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value
pic10f220/222 ds41270b-page 44 preliminary ? 2006 microchip technology inc. table 9-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f,d f,d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z none z none z z none none c c c,dc,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k k k k k ? k ? f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none to , pd none z none none none to , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a ? 0 ? by any instruction that writes to the pc except for goto . see section 4.7 ?program counter? . 2: when an i/o register is modified as a function of itself (e.g., movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 3: the instruction tris f , where f = 6 causes the contents of the w register to be written to the tri-state latches of portb. a ? 1 ? forces the pin to a high-impedance state and disables the output buffers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared (if assigned to tmr0).
? 2006 microchip technology inc. preliminary ds41270b-page 45 pic10f220/222 9.1 instruction description addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register and register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) (w) status affected: z description: the contents of the w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d [0,1] operation: (w) and (f) (destination) status affected: z description: the contents of the w register are and?ed with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruc- tion fetched during the current instruction execution is discarded, and a nop is executed instead, making this a 2-cycle instruction.
pic10f220/222 ds41270b-page 46 preliminary ? 2006 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruc- tion fetched during the current instruction execution, is discarded and a nop is executed instead, making this a 2-cycle instruction. call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 top of stack; k pc<7:0>; (status<6:5>) pc<10:9>; 0 pc<8> status affected: none description: subroutine call. first, return address (pc + 1) is pushed onto the stack. the eight-bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from status<6:5>, pc<8> is cleared. call is a two- cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h (f); 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w); 1 z status affected: z description: the w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt k operands: none operation: 00h wdt; 0 wdt prescaler (if assigned); 1 to; 1 pd status affected: to , pd description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d [0,1] operation: (f ) (dest) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2006 microchip technology inc. preliminary ds41270b-page 47 pic10f220/222 decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 (dest) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d [0,1] operation: (f) ? 1 d; skip if result = 0 status affected: none description: the contents of register ?f? are dec- remented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, the next instruc- tion, which is already fetched, is discarded and a nop is executed instead making it a two-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k pc<8:0>; status<6:5> pc<10:9> status affected: none description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 0 ?, then the next instruction, which is already fetched, is discarded and a nop is executed instead making it a two- cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register.
pic10f220/222 ds41270b-page 48 preliminary ? 2006 microchip technology inc. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d [0,1] operation: (w).or. (f) (dest) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. movf move f syntax: [ label ] movf f,d operands: 0 f 31 d [0,1] operation: (f) (dest) status affected: z description: the contents of register ?f? are moved to destination ?d?. if ?d? is ? 0 ?, destination is the w register. if ?d? is ? 1 ?, the destination is file register ?f?. ?d? = 1 is useful as a test of a file register, since status flag z is affected. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none description: the eight-bit literal ?k? is loaded into the w register. the ?don?t cares? will assembled as ? 0 ?s. movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) (f) status affected: none description: move data from the w register to register ?f?. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. option load option register syntax: [ label ] option operands: none operation: (w) option status affected: none description: the content of the w register is loaded into the option register.
? 2006 microchip technology inc. preliminary ds41270b-page 49 pic10f220/222 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none description: the w register is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. c register ?f? c register ?f? sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt; 0 wdt prescaler; 1 to ; 0 pd status affected: to , pd, rbwuf description: time-out status bit (to ) is set. the power-down status bit (pd ) is cleared. rbwuf is unaffected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see section on sleep for more details. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 31 d [0,1] operation: (f) ? (w) ( dest) status affected: c, dc, z description: subtract (2?s complement method) the w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d [0,1] operation: (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w register. if ?d? is ? 1 ?, the result is placed in register ?f?.
pic10f220/222 ds41270b-page 50 preliminary ? 2006 microchip technology inc. tris load tris register syntax: [ label ] tris f operands: f = 6 operation: (w) tris register f status affected: none description: tris register ?f? (f = 6 or 7) is loaded with the contents of the w register xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2006 microchip technology inc. preliminary ds41270b-page 51 pic10f220/222 10.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +125c storage temperature ............................................................................................................ ...................-65c to +150c voltage on v dd with respect to v ss ..................................................................................................................0 to +6.5v voltage on mclr with respect to v ss .............................................................................................................0 to +13.5v voltage on all other pins with respect to v ss .................................................................................. -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... ......200 mw max. current out of v ss pin ........................................................................................................................... ..........80 ma max. current into v dd pin ........................................................................................................................... .............80 ma input clamp current, i ik (v i < 0 or v i > v dd ) ...................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) .............................................................................................................. 20 ma max. output current sunk by any i/o pin ........................................................................................ .........................25 ma max. output current sourced by any i/o pin ..................................................................................... .......................25 ma max. output current sourced by i/o port ....................................................................................... ..........................75 ma max. output current sunk by i/o port .......................................................................................... ............................75 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } .. + (v ol x i ol ) ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
pic10f220/222 ds41270b-page 52 preliminary ? 2006 microchip technology inc. figure 10-1: voltage-frequency graph, -40 c t a +125 c 6.0 2.5 4.0 3.0 0 3.5 4.5 5.0 5.5 410 frequency (mhz) v dd 20 (volts) 25 2.0 8
? 2006 microchip technology inc. preliminary ds41270b-page 53 pic10f220/222 10.1 dc characteristics: pic10f220/222 (industrial) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) param no. sym characteristic min typ (1) max units conditions d001 v dd supply voltage 2.0 ? 5.5 v see figure 10-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?vss? vsee section 8.4 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 8.4 ?power-on reset (por)? for details d010 i dd supply current (3) ? ? ? ? 170 350 250 450 tbd tbd tbd tbd a a a a f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v f osc = 8 mhz, v dd = 2.0v f osc = 8 mhz, v dd = 5.0v d020 i pd power-down current (4) ?0.1tbd av dd = 2.0v d022 i wdt wdt current (4) ?1.0tbd av dd = 2.0v d024 i adc a/d current ?80tbd av dd = 2.0v legend: tbd = to be determined. * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss .
pic10f220/222 ds41270b-page 54 preliminary ? 2006 microchip technology inc. 10.2 dc characteristics: pic10f220/222 (extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +125 c (extended) param no. sym characteristic min typ (1) max units conditions d001 v dd supply voltage 2.0 5.5 v see figure 10-1 d002 v dr ram data retention voltage (2) ? 1.5* ? v device in sleep mode d003 v por v dd start voltage to ensure power-on reset ?vss? vsee section 8.4 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure power-on reset 0.05* ? ? v/ms see section 8.4 ?power-on reset (por)? for details d010 i dd supply current (3) ? ? ? ? 170 350 250 450 tbd tbd tbd tbd a a a a f osc = 4 mhz, v dd = 2.0v f osc = 4 mhz, v dd = 5.0v f osc = 8 mhz, v dd = 2.0v f osc = 8 mhz, v dd = 5.0v d020 i pd power-down current (4) ?0.1tbd av dd = 2.0v d022 i wdt wdt current (4) ?1.0tbd av dd = 2.0v d024 i adc a/d current ?80tbd av dd = 2.0v legend: tbd = to be determined. * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, bus rate, internal code execution pattern and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: all i/o pins tri-stated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as specified. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss .
? 2006 microchip technology inc. preliminary ds41270b-page 55 pic10f220/222 table 10-1: dc characteristics: pic10f220/222 (industrial, extended) dc characteristics standard operating conditions (unless otherwise specified) operating temperature-40c t a +85c (industrial) -40c t a +125c (extended) operating voltage v dd range as described in dc specification param no. sym characteristic min typ? max units conditions v il input low voltage i/o ports: d030 with ttl buffer vss ? 0.8v v for all 4.5 v dd 5.5v d030a vss ? 0.15 v dd v otherwise d031 with schmitt trigger buffer vss ? 0.15 v dd v d032 mclr , t0cki vss ? 0.15 v dd v v ih input high voltage i/o ports: ? d040 with ttl buffer 2.0 ? v dd v4.5 v dd 5.5v d040a 0.25 v dd + 0.8v ?v dd v otherwise d041 with schmitt trigger buffer 0.85 v dd ?v dd v for entire v dd range d042 mclr , t0cki 0.85 v dd ?v dd v d070 i pur gpio weak pull-up current tbd 250 tbd av dd = 5v, v pin = v ss i il input leakage current (1), (2) d060 i/o ports ? ? 1 a vss v pin v dd , pin at high-impedance d061 gp3/mclr (3) ?? 5 a vss v pin v dd output low voltage d080 i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v, -40 c to +85 c d080a ? ? 0.6 v i ol = 7.0 ma, v dd = 4.5v, +85 c to +125 c output high voltage d090 i/o ports (2) v dd ?0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v, -40 c to +85 c d090a v dd ?0.7 ? ? v i oh = -2.5 ma, v dd = 4.5v, +85 c to +125 c capacitive loading specs on output pins d101 all i/o pins ? ? 50* pf legend: tbd = to be determined. ? data in ?typ? column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. * these parameters are for desi gn guidance only and are not tested. note 1: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 2: negative current is defined as coming out of the pin. 3: this specification applies when gp3/mclr is configured as an input with pull-up disabled. the leakage current of the mclr circuit is higher than the standard i/o logic.
pic10f220/222 ds41270b-page 56 preliminary ? 2006 microchip technology inc. table 10-2: pull-up resistor ranges v dd (volts) temperature ( c) min typ max units gp0/gp1 2.0 -40 tbd 91k tbd 25 tbd 105k tbd 85 tbd 118k tbd 125 tbd 125k tbd 5.5 -40 tbd 18k tbd 25 tbd 23k tbd 85 tbd 26k tbd 125 tbd 28k tbd gp3 2.0 -40 tbd 63k tbd 25 tbd 74k tbd 85 tbd 83k tbd 125 tbd 87k tbd 5.5 -40 tbd 16k tbd 25 tbd 21k tbd 85 tbd 25k tbd 125 tbd 27k tbd legend: tbd = to be determined. * these parameters are characterized but not tested.
? 2006 microchip technology inc. preliminary ds41270b-page 57 pic10f220/222 10.3 timing parameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: figure 10-2: load conditions table 10-3: calibrated internal rc frequencies 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2to mcmclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial), -40 c t a +125 c (extended) param no. sym characteristic freq. tolerance min typ? max units conditions f10 f osc internal calibrated intosc frequency (1), (2) 1% 7.92 8 8.08 mhz 3.5v @ ta = 25c 2% 7.84 8 8.16 mhz 2.5v v dd 5.5v temperature 0-85 c 5% 7.60 8 8.4 mhz 2.0v v dd 5.5v -40 c t a +85 c (industrial) -40 c t a +125 c (extended) legend: tbd = to be determined. * these parameters are characterized but not tested. ? data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 f and 0.01 f values in parallel are recommended. 2: the 4 mhz clock is derived from the 8 mhz oscillator. to obtain 4 mhz tolerance values, divide the appropriate 8 mhz value by 2. c l v ss pin legend: c l = 50 pf for all pins
pic10f220/222 ds41270b-page 58 preliminary ? 2006 microchip technology inc. figure 10-3: reset, watchdog timer and device reset timer timing table 10-4: reset, watchdog timer and device reset timer figure 10-4: timer0 clock timings ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) -40 c t a +125 c (extended) param no. sym characteristic min typ (1) max units conditions 30 t mc lmclr pulse width (low) 2000* ? ? ns v dd = 5.0v 31 t wdt watchdog timer time-out period (no prescaler) 9* 9* 18* 18* 30* 40* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 32 t drt device reset timer period 0.5* 0.5* 1.125* 1.125* 2* 2.5* ms ms v dd = 5.0v (industrial) v dd = 5.0v (extended) 34 t ioz i/o high-impedance from mclr low ? ? 2000* ns * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt timeout (2) internal reset watchdog timer reset 32 31 34 i/o pin (1) 32 32 34 30 note 1: i/o pins must be taken out of high-impedance mode by enabling the output drivers in software. 2: runs on por reset only. t0cki 40 41 42
? 2006 microchip technology inc. preliminary ds41270b-page 59 pic10f220/222 table 10-5: timer0 clock requirements table 10-6: a/d converter characteristics (pic10f220) ac characteristics standard operating conditions (unless otherwise specified) operating temperature -40 c t a +85 c (industrial) -40 c t a +125 c (extended) param no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 41 tt0l t0cki low pulse width no prescaler 0.5 t cy + 20* ? ? ns with prescaler 10* ? ? ns 42 tt0p t0cki period 20 or t cy + 40* n ? ? ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (?typ?) column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 8 bits bit a02 e abs total absolute error* (1) ?? tbdlsbv dd = 5.0v a03 e il integral error ? ? 1 lsb v dd = 5.0v a04 e dl differential error ? ? -1 < e dl + 1.0 lsb no missing codes to 8 bits v dd = 5.0v a05 e fs full-scale range 2.0* ? 5.5* v v dd a06 e off offset error ? ? 1 lsb v ref = 5.0v a07 e gn gain error ? ? 1 lsb v ref = 5.0v a10 ? monotonicity ? guaranteed (2) ??v ss v ain v dd a25 v ain analog input voltage v ss ?v dd v a30 z ain recommended impedence of analog voltage source ?? 10 k * these parameters are characterized but not tested. ? data in the ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: v ref current is from external v ref or v dd pin, whichever is selected as reference input. 4: when a/d is off, it will not consume any current other than leakage current. the power-down current specification includes any such leakage from the a/d module.
pic10f220/222 ds41270b-page 60 preliminary ? 2006 microchip technology inc. table 10-7: a/d converter characteristics (pic10f222) table 10-8: pic10f220/222 a/d conversion requirements param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 8 bits bit a03 e il integral error ? ? 1 lsb v dd = 5.0v a04 e dl differential error ? ? -1 < e dl + 1.0 lsb no missing codes to 8 bits v dd = 5.0v a05 e fs full-scale range 2.0* ? 5.5* v v dd a06 e off offset error ? ? 1 lsb v ref = 5.0v a07 e gn gain error ? ? 1 lsb v ref = 5.0v a10 ? monotonicity ? guaranteed (1) ??v ss v ain v dd a25 v ain analog input voltage v ss ?v dd v a30 z ain recommended impedence of analog voltage source ?? 10 k * these parameters are characterized but not tested. ? data in the ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only are not tested. note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. sym characteristic min typ? max units conditions ad131 t cnv conversion time (not including acquisition time) (1) ?13?t cy set go/done bit to new data in a/d result register ad132* t acq acquisition time ? 3.5 5 ? s s v dd = 5v v dd = 2.5v * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
? 2006 microchip technology inc. preliminary ds41270b-page 61 pic10f220/222 11.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer ? low-cost demonstration and development boards and evaluation kits 11.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic10f220/222 ds41270b-page 62 preliminary ? 2006 microchip technology inc. 11.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 11.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 family of microcontrollers and dspic30f family of digital signal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 11.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 11.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 11.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the picmicro mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, as well as internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
? 2006 microchip technology inc. preliminary ds41270b-page 63 pic10f220/222 11.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 11.8 mplab ice 4000 high-performance in-circuit emulator the mplab ice 4000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end picmicro mcus and dspic dscs. software control of the mplab ice 4000 in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, and up to 2 mb of emulation memory. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 11.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost-effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 11.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications.
pic10f220/222 ds41270b-page 64 preliminary ? 2006 microchip technology inc. 11.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 11.12 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various picmicro mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart ? battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) and the latest ?product selector guide? (ds00148) for the complete list of demonstration, development and evaluation kits.
? 2006 microchip technology inc. preliminary ds41270b-page 65 pic10f220/222 12.0 dc and ac characteristics graphs and charts graphs and charts are not available at this time.
pic10f220/222 ds41270b-page 66 preliminary ? 2006 microchip technology inc. notes:
? 2006 microchip technology inc. preliminary ds41270b-page 67 pic10f220/222 13.0 packaging information 13.1 package marking information 6-lead sot-23 xxnn example ch17 xxxxxnnn 8-lead pdip xxxxxxxx yyww 017 example 10f222/p 0410 * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e
pic10f220/222 ds41270b-page 68 preliminary ? 2006 microchip technology inc. 6-lead plastic small outline transistor (ot) (sot-23) 1 d b n e e1 l c a2 a a1 p1 10 5 0 10 5 0 mold draft angle bottom 10 5 0 10 5 0 mold draft angle top 0.50 0.43 0.35 .020 .017 .014 b lead width 0.20 0.15 0.09 .008 .006 .004 c lead thickness 10 5 0 10 5 0 foot angle 0.55 0.45 0.35 .022 .018 .014 l foot length 3.10 2.95 2.80 .122 .116 .110 d overall length 1.75 1.63 1.50 .069 .064 .059 e1 molded package width 3.00 2.80 2.60 .118 .110 .102 e overall width 0.15 0.08 0.00 .006 .003 .000 a1 standoff 1.30 1.10 0.90 .051 .043 .035 a2 molded package thickness 1.45 1.18 0.90 .057 .046 .035 a overall height 1.90 bsc .075 bsc p1 outside lead pitch 0.95 bsc .038 bsc p pitch 6 6 n number of pins max nom min max nom min dimension limits millimeters inches * units dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .005" (0.127mm) per s ide. notes: jeita (formerly eiaj) equivalent: sc-74a * controlling parameter drawing no. c04-120 bsc: basic dimension. theoretically exact value shown without tolerances. see asme y14.5m revised 09-12-05
? 2006 microchip technology inc. preliminary ds41270b-page 69 pic10f220/222 8-lead plastic dual in-line (p) ? 300 mil body (pdip) b1 b a1 a l a2 p e eb c e1 n d 1 2 units inches * millimeters dimension limits min nom max min nom max number of pins n 88 pitch p .100 2.54 top to seating plane a .140 .155 .170 3.56 3.94 4.32 molded package thickness a2 .115 .130 .145 2.92 3.30 3.68 base to seating plane a1 .015 0.38 shoulder to shoulder width e .300 .313 .325 7.62 7.94 8.26 molded package width e1 .240 .250 .260 6.10 6.35 6.60 overall length d .360 .373 .385 9.14 9.46 9.78 tip to seating plane l .125 .130 .135 3.18 3.30 3.43 lead thickness c .008 .012 .015 0.20 0.29 0.38 upper lead width b1 .045 .058 .070 1.14 1.46 1.78 lower lead width b .014 .018 .022 0.36 0.46 0.56 overall row spacing eb .310 .370 .430 7.87 9.40 10.92 mold draft angle top 51015 51015 mold draft angle bottom 51015 51015 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per si de. jedec equivalent: ms-001 drawing no. c04-018 significant characteristic
pic10f220/222 ds41270b-page 70 preliminary ? 2006 microchip technology inc. appendix a: revision history revision a original release of document. revision b (03/2006) table 3-1, gp1; section 4.7, program counter; table 5- 2; figure 8-5; section 9.1, andwf, sleep, subwf, swapf, xorlw.
? 2006 microchip technology inc. preliminary ds41270b-page 71 pic10f220/222 index a alu ..................................................................................... 11 assembler mpasm assembler..................................................... 64 b block diagram on-chip reset circuit ................................................. 38 timer0......................................................................... 27 tmr0/wdt prescaler................................................. 30 watchdog timer.......................................................... 41 brown-out protection circuit .............................................. 42 c c compilers mplab c18 ................................................................ 64 mplab c30 ................................................................ 64 carry ................................................................................... 11 clocking scheme ................................................................ 13 code protection ............................................................ 35, 43 configuration bits................................................................ 35 customer change notification service ............................... 75 customer notification service............................................. 75 customer support............................................................... 75 d dc and ac characteristics ................................................. 67 development support ......................................................... 63 digit carry ........................................................................... 11 e errata .................................................................................... 5 f family of devices pic10f22x ................................................................... 7 fsr ..................................................................................... 22 i i/o interfacing ..................................................................... 23 i/o ports .............................................................................. 23 i/o programming considerations........................................ 25 id locations .................................................................. 35, 43 indf.................................................................................... 22 indirect data addressing..................................................... 22 instruction cycle ................................................................. 13 instruction flow/pipelining .................................................. 13 instruction set summary..................................................... 46 internet address.................................................................. 75 l loading of pc ..................................................................... 21 m memory organization.......................................................... 15 data memory .............................................................. 16 program memory (pic10f220/222)............................ 15 microchip internet web site ................................................ 75 mplab asm30 assembler, linker, librarian ..................... 64 mplab icd 2 in-circuit debugger ..................................... 65 mplab ice 2000 high-performance universal in-circuit emulator ...................................................... 65 mplab ice 4000 high-performance universal in-circuit emulator ...................................................... 65 mplab integrated development environment software.... 63 mplab pm3 device programmer ...................................... 65 mplink object linker/mplib object librarian .................. 64 o option register................................................................ 19 osccal register............................................................... 20 oscillator configurations................ ..................................... 36 oscillator types hs............................................................................... 36 lp ............................................................................... 36 p pic10f220/222 device varieties.......................................... 9 picstart plus development programmer....................... 66 por device reset timer (drt) ................................... 35, 40 pd ............................................................................... 41 power-on reset (por)............................................... 35 to ............................................................................... 41 portb ............................................................................... 23 power-down mode.............................................................. 42 prescaler ............................................................................ 29 program counter ................................................................ 21 q q cycles .............................................................................. 13 r reader response............................................................... 76 read-modify-write.............................................................. 25 register file map pic10f220 ................................................................. 16 pic10f222 ................................................................. 16 registers special function ......................................................... 17 reset .................................................................................. 35 reset on brown-out ........................................................... 42 s sleep ............................................................................ 35, 42 software simulator (mplab sim) ...................................... 64 special features of the cpu .............................................. 35 special function registers ................................................. 17 stack................................................................................... 21 status register ....................................................... 11, 18, 31 t timer0 timer0 ........................................................................ 27 timer0 (tmr0) module .............................................. 27 tmr0 with external clock .......................................... 28 timing parameter symbology and load conditions .......... 59 tris registers ................................................................... 23 w wake-up from sleep ........................................................... 43 watchdog timer (wdt)................................................ 35, 40 period ......................................................................... 40 programming considerations ..................................... 40 www address ................................................................... 75 www, on-line support .................... ................................... 5
pic10f220/222 ds41270b-page 72 preliminary ? 2006 microchip technology inc. z zero bit ................................................................................ 11
? 2006 microchip technology inc. preliminary ds41270b-page 73 pic10f220/222 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
pic10f220/222 ds41270b-page 74 preliminary ? 2006 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41270b pic10f220/222 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2006 microchip technology inc. preliminary ds41270b-page 75 pic10f220/222 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic10f220 (1) , pic10f222 (1) ; v dd range 2.0v to 5.5v temperature range: i= -40 c to +85 c (industrial) e= -40 c to +125 c (extended) package: ot = sot, 6-ld (pb-free) p = 300 mil pdip, 8-ld (pb-free) pattern: special requirements examples: a) pic10f220 ? i/p = industrial temp., pdip package (pb-free) b) pic10f222 ? t-i/ot = industrial temp., sot package (pb-free) note 1: sot packages are only available in tape and reel.
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